The present invention generally relates to semiconductor device manufacturing, and more particularly to the formation of a protective liner between a gate contact (CB) and a gate dielectric.
Forming electrical contacts to the terminals of integrated circuit transistors becomes more challenging as the transistors become smaller and more complex. Transistor designs such as fin field-effect-transistors (FinFETs) pose new challenges to circuit designers in positioning component structures that are prone to copper poisoning of silicon. Typically, modern technology requires introduction of copper (Cu) material into middle-of-line (MOL) levels to reduce MOL resistance. A Cu fin contact can directly connect to a trench silicide which uses non-Cu material (e.g., W or Co). A Cu gate contact typically connects directly to a metal gate having a gate dielectric (high-k) and work function metal (WFM).